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Si9118/Si9119
New Product
Vishay Siliconix
Programmable Duty Cycle Controller
FEATURES
D D D D 10- to 200-V Input Range Current-Mode Control Internal Start-Up Circuit Buffer Slope Compensation Voltage D D D D Soft-Start 2.7-MHz Error Amp 500-mA Output Drive Current Light Load Frequency Fold-Back D Low Quiescent Current D Programmable Maximum Duty Cycle, with 80% as Default
DESCRIPTION
The Si9118/Si9119 are a BiC/DMOS current-mode pulse width modulation (PWM) controller ICs for high-frequency dc/dc converters. Single-ended topologies (forward and flyback) can be implemented at frequencies up to 1 MHz. The controller operates in constant frequency mode during the full load and automatically switches to pulse skipping mode under light load to maintain high efficiency throughout the full load range. The maximum duty cycle is easily programmed with a resistor divider for optimum control. The push-pull output driver provides high-speed switching to external MOSPOWER devices large enough to supply 50 W of output power. Shoot-through current for internal push-pull stage is almost eliminated to minimize quiescent supply current. The high-voltage DMOS transistor permits direct operation from bus voltages of up to 200 V. Other features include a 1.5% accurate voltage reference, 2.7-MHz bandwidth error amplifier, standby mode, soft-start and undervoltage lockout circuits. The Si9118/Si9119 are available in a 16-pin SOIC package and is specified over the industrial, D suffix (-40_C to 85_C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
VSC (Si9118) SYNC (Si9119) 12
FB 5 Error Amplifier 4 - +
COMP 6
ILIMIT 10
ICS PWM/PSM 11 2
DMAX 13 9
1.0 - 2.0 V +- - +
PWM
ROSC COSC
OSC
8
NI
3 VREF
Ref Gen 4.6 V 23 mA 100 mV Pulse Skip + EN - IMAX 600 mV -VIN + - Substrate R Q S 14 -VIN 15
DR
SS/EN
7
VCC
16
+VIN
1 - - + + 8.6 V
- + 9.3 V (VREG) Undervoltage Lockout
Document Number: 70815 S-60752--Rev. B, 05 Apr-99
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Si9118/Si9119
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V +VIN (Note: VCC < +VIN + 0.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Logic Input (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Linear Inputs (FB, ICS, ILIMIT, SS/EN) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C DMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 V Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 16-Pin SOIC (Y Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (QJA) 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mW/_C above 25_C.
New Product
* . Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time.
RECOMMENDED OPERATING RANGE
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 16.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 200 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 kW to 1 MW COSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 pF to 200 pF Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 4 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONS
Test Conditions Unless Specified Parameter Reference
OSC Disabled, TA = 25_C O t t V lt Output Voltage Short Circuit Current Load Regulation VREF ISREF DVR/DIR OSC Disabled, Over Voltage and Temperature Rangesc VREF = -VIN IREF = 0 to -1 mA Room Full 3.94 3.88 4.0 4.0 -30 10 4.06 4.12 -5 40 V mA mV
Limits
D Suffix -40 to 85_C
Symbol
Oscillator Disabled O ill t Di bl d -VIN = 0 V, VCC = 10 V
Tempa
Min
Typb
Max
Unit
Oscillator
Initial Accuracyd Voltage Stabilityc Temperature Coefficientc Sync High Pulse Width (Si9119) Sync Low Pulse Width (Si9119) Sync Rise/Fall Time (Si9119) Sync Logic Low (Si9119) Sync Logic High (Si9119) Sync Rangec (Si9119) VIL VIH fEXT 4 1.05 x fOSC fOSC fOSCc Df/f OSC TC ROSC = 374 kW, COSC = 200 pF ROSC = 70 kW, COSC = 200 pF ROSC = 70 kW, COSC = 200 pF Df/f = [f(16.5 V) - f(9.5 V)] / f(9.5 V) -40 v TA v 85_C, fOSC = 100 kHz 200 200 200 0.8 V kHz ns 90 450 100 500 1 200 110 550 2 500 kHz % ppm/_C
PWM/PSM
PWM/PSM Logic High PWM/PSM Logic Low VIH VIL 4 0.8 V
DMAX
Accuracy www.Vishay Siliconix.com S FaxBack 408-970-5600 fOSC = 100 kHz with 1% Resistor "10 %
2
Document Number: 70815 S-60752--Rev. B, 05 Apr-99
Si9118/Si9119
New Product
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified Parameter Error Amplifier (OSC Disabled)
Input BIAS Current Input OFFSET Voltage Open Loop Voltage Gainc Unity Gain Bandwidthc Output Current Power Supply Rejection IFB VOS2 AVOL BW IOUT PSRR Source (VFB = 3.5 V, NI = VREF) Sink (VFB = 4.5 V, NI = VREF) 10 V v VCC v 16.5 V 65 1.8 -1.0 1.0 50 VFB = 5 V, NI = VREF t1.0 "5 80 2.7 -2.7 2.4 80 "200 "25 nA mV dB MHz mA dB
Limits
D Suffix -40 to 85_C
Symbol
O ill t Di bl d Oscillator Disabled -VIN = 0 V, VCC = 10 V
Tempa
Min
Typb
Max
Unit
Pre-Regulator/Start-up
Input Voltagec Input Leakage Current Pre-Regulator Start-Up Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG -VUVLO +VIN +IIN ISTART VREG VUVLO VDELTA IIN = 10 mA VCC w 10 V Pulse Width v 300 ms VCC = VULVO IPRE-REGULATOR = 15 mA Room Room Room Room Room Room 8 8.7 8.0 0.3 15 9.3 8.6 0.7 9.8 9.3 V 200 10 V mA mA
Supply
Supply Current ICC CLOAD v 50 pF, fOSC = 100 kHz 1.9 2.5 mA
Protection
Current Limit Threshold Voltage Current Limit Delay to Outputc Soft-Start Current Output Inhibit Voltage Pulse Skipping Threshold Voltage VI(Limit) td ISS VSS(off) VPS Soft-Start Voltage to Disable Driver Output VFB = 0 V, NI = VREF VSENSE = 0.85 V, See Figure 1 -12 0.5 80 0.5 0.6 77 -23 1.26 100 120 0.7 100 -30 V ns mA V mV
Mosfet Driver
Output High Voltage Output Low Voltage Output Resistancec Rise Timec Fall Timec VOH VOL ROUT tr tf IOUT = -10 mA IOUT = 10 mA IOUT = 10 mA, Source or Sink CL = 500 pF Room Full Room Full Room Full Room Room 20 25 40 40 VCC - 0.3 VCC - 0.5 0.3 0.5 30 50 75 75 V
W ns
Notes a. Room = 25_C, Full = as determined by the operating temperature suffix. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Guaranteed by design, not subject to production test. d. CSTRAY v 5 pF on COSC.
Document Number: 70815 S-60752--Rev. B, 05 Apr-99
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Si9118/Si9119
Vishay Siliconix
New Product
MOSFET
Output Driver Rise and Fall Time
200 47 pF Output Rise and Fall Time (ns) 100 pF 150 pF 200 pF f OUT (kHz) tr for CL = 2500 pF 150
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Oscillator Frequency
2 x 1000
tf for CL = 2500 pF 100 tr for CL = 1000 pF tf for CL = 1000 pF tr 10% to 90% tf 90% to 10% 0
2 x 100
Note: These curves were measured in a board with 3.5 pF of external parasitic capacitance. 2 x 10 10 100 rOSC - Oscillator Resistance (kW) 1000
50
9
10
11 12 13 14 15 VCC - Supply Voltage (V)
16
17
Supply Current vs. Output Frequency
36 32 28 I CC - Supply Current (mA) I CC - Supply Current (mA) 24 CL = 2500 pF 20 16 12 8 CL = 0 pF 4 0 0 200 400 600 800 fOUT - Output Frequency (kHz) 1000 0 CL = 1000 pF VCC = 12 V COSC = 47 pF 9 12
Supply Current vs. Supply Voltage
ROSC = 127 kW COSC = 47 pF fs = 500 kHz CL = 1000 pF
6
3
CL = 0 pF
9
10
11 12 13 14 15 VCC - Supply Voltage (V)
16
17
Switching Frequency vs. Supply Voltage
1.05 ROSC = 56 kW COSC = 100 pF 1.00 Switching Frequency (MHz)
0.95
0.90
0.85
8
9
10
11 12 13 14 15 VCC - Supply Voltage (V)
16
17
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Document Number: 70815 S-60752--Rev. B, 05 Apr-99
Si9118/Si9119
New Product
TIMING WAVEFORMS
tr v 10 ns 0.85 Current Sense 50% 0 td Output VCC
Vishay Siliconix
90% 0
FIGURE 1.
PIN CONFIGURATIONS
+VIN PWM/PSM VREF NI FB COMP SS/EN COSC
1 2 3 4 5 6 7 8
16 15 14
VCC DR -VIN DMAX VSC ICS ILIMIT ROSC COMP
+VIN PWM/PSM VREF NI FB
1 2 3 4 5 6
16 15 14
VCC DR -VIN DMAX SYNC ICS ILIMIT ROSC Order Number SOIC: SI9118DY Si9119DY
SOIC SI9118DY
Top View
13 12 11 10 9
SOIC Si9119DY
Top View
13 12 11 10 9
SS/EN COSC
7 8
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Document Number: 70815 S-60752--Rev. B, 05 Apr-99
Symbol
+VIN PWM/PSM VREF NI FB COMP SS/EN COSC ROSC ILIMIT ICS SYNC or VSC DMAX -VIN DR VCC Input bus voltage ranging from 10 V to 200 V.
Description
Connected to VREF forces the converter into PWM mode. Connected to -VIN forces the converter into PSM mode. 4-V reference voltage. Decouple with 0.1-mF ceramic capacitor. Non-inverting input of an error amplifier. Inverting input of an error amplifier. Error amplifier output for external compensation network. Programmable soft-start with external capacitor or externally controlled disable mode. External capacitor to determine the switching frequency. External resistor to determine the switching frequency. Pulse by pulse peak current limiting pin. When the current sense voltage exceeds the current limit threshold, the gate drive signal is terminated. ILIMIT is also used to sense the current in pulse skipping mode. Current sense input to control feedback response. Si9118: slope compensation pin. Si9119: clock synchronization pin. Logic high to low transition from external signal synchronizes the internal clock frequency. Sets the maximum duty cycle. Internally, the maximum duty cycle is clamped to 80%. Single point ground. Gate drive for the external MOSFET switch. Supply voltage for the IC after the startup transition. www.Vishay Siliconix.com S FaxBack 408-970-5600
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Si9118/Si9119
Vishay Siliconix
STANDARD APPLICATION CIRCUITS
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VO
+VIN VCC PWM/PSM ICS VREF DR NI -VIN DMAX FB VSC COMP COSC SS/EN ILIMIT ROSC
Si9420DY
TL431
-48 V (-42 to -56 V)
FIGURE 2. Si9118 15-W Forward Converter Schematic
VO
+VIN VCC PWM/PSM ICS VREF DR NI -VIN DMAX FB SYNC COMP COSC SS/EN ILIMIT ROSC
Si9420DY
TL431
-48 V (-42 to -56 V)
FIGURE 3. Si9119 Forward Converter With External Slope Compensation
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Document Number: 70815 S-60752--Rev. B, 05 Apr-99
Si9118/Si9119
New Product
DETAILED OPERATIONAL DESCRIPTION
Start-Up Si9118/Si9119 are designed with internal depletion mode MOSFET capable of powering directly from the high input bus voltage. This feature eliminates the typical external start-up circuit saving valuable space and cost. But, most of all, this feature improves the converter efficiency during full load and has an even greater impact on light load. With an input bus voltage applied to the +VIN pin, the VCC voltage is regulated to 9.3 V. The UVLO circuit prevents the controller output driver section from turning on, until VCC voltage exceeds 8.7 V. In order to maximize converter efficiency, the designer should provide an external bootstrap winding to override the internal VCC regulator. If external VCC voltage is greater than 9.3 V, the internal depletion mode MOSFET regulator is disabled and power is derived from the external VCC supply. The VCC supply provides power to the internal circuity as well as providing supply voltage to the gate drive circuit. Soft-Start/Enable The soft-start time is externally programmable with capacitor connected to the SS/EN pin. A constant current source provides the current to the SS/EN pin to generate a linear start-up time versus the capacitance value. The SS/EN pin clamps the error amplifier output voltage, limiting the rate of increase in duty cycle. By controlling the rate of rise in duty cycle gradually, the output voltage rises gradually preventing the output voltage from overshooting. The SS/EN pin can also be used to enable or disable the output driver section with an external logic signal. Synchronization The synchronization to external clock is easily accomplished by connecting the external clock into the SYNC pin (Si9119 only). The logic high to low transition synchronizes the clock. The external clock frequency must be at least 5% faster than the internal clock frequency. Reference Voltage The reference voltage for the Si9118/Si9119 are set at 4.0 V. The reference voltage is not connected to the non-inverting inputs of the error amplifier, therefore, the minimum output voltage is not limited to reference voltage. The VREF pin requires a 0.1-mF decoupling capacitor. Error Amplifier The error amplifier gain-bandwidth product is critical parameter which determines the transient response of converter. The transient response is function of both small and large signal responses. The small signal response is determined by the feedback compensation network while the large signal response is determined by the inductor di/dt slew rate. Besides the
Document Number: 70815 S-60752--Rev. B, 05 Apr-99
Vishay Siliconix
inductance value, the error amplifier gain-bandwidth determines the converter response time. In order to minimize the response time, Si9118/Si9119 is designed with a 2.7-MHz error amplifier gain-bandwidth product to provide the widest converter bandwidth possible. PWM Mode The converter operates in PWM mode if the PWM/PSM pin is connected to VREF pin or logic high. As the load current and line voltage vary, the Si9118/Si9119 maintain constant switching frequency until they reach minimum duty cycle. Once the output voltage regulation is exceeded with minimum duty cycle, the switching frequency will continue to decrease until regulation is achieved. The switching frequency is controlled by the external Rosc and Cosc as shown by the typical oscillator frequency curve. In PWM mode, output ripple noise is constant reducing EMI concerns as well as simplifying the filter to minimize the system noise. Pulse Skipping Mode If the PWM/PSM pin is connected to -VIN pin (logic low), the converter can operate in either PWM or PSM mode depending on the load current. The converter automatically transitions from PWM to PSM or vise versa to maintain output voltage regulation. In PSM mode, the MOSFET switch is turned on until the peak current sensed voltage reaches 100 mV and the output voltage meets or exceeds its regulation voltage. The converter is operating in pulse skipping mode because each pulse delivers excess energy into the output capacitor forcing the output voltage to exceed its regulation voltage. By forcing the output voltage to exceed the regulation voltage, succeeding pulses are skipped until the output voltage drops below the regulation point. Therefore, switching frequency will continue to reduce during PSM control as the demand for output current decreases. The pulse skipping mode cuts down the switching losses, the dominant power consumed during low output current, thereby maintaining high efficiency throughout the entire load range. With PWM/PSM pin in logic low state, the converter transitions back into PWM mode, if the peak current sensed voltage of 100 mV does not generate the required output voltage. In the region between pulse skipping mode and PWM mode, the controller may transition between the two modes, delivering spurts of pulses. This may cause the current waveform to look irregular, but this will not overly affect the ripple voltage. Even in this transitional mode, efficiency remains high. Programmable Duty Cycle Control The maximum duty cycle limit is controlled by the voltage on DMAX pin. A DMAX voltage of 3.2 V generates 80% duty cycle while 0.0 V generates 0% duty cycle. The 80% duty cycle is maximum default condition at 1-MHz switching frequency. The DMAX voltage can be easily generated using resistor divider from the reference voltage.
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Si9118/Si9119
Vishay Siliconix
New Product
DETAILED OPERATIONAL DESCRIPTION (CONT'D)
The maximum duty cycle limitation will be different when the converter is synchronized by an external frequency. If the internal free running frequency is much slower than the external SYNC signal (SYNC signal causes the internal clock to reset before the Cosc voltage ramps to 3.2 V) , duty cycle is determined by the one shot discharge time of the oscillator capacitor (100 ns). Therefore, with 1-MHz SYNC signal, maximum duty cycle of 90% can be achieved (100 ns is 10% of 1 MHz). If the internal free running frequency is very close to the external SYNC frequency (SYNC signal causes the internal clock to reset somewhere between 3.2 V to 4 V), duty cycle is determined by the ratio of Cosc voltage at the SYNC point and the 3.2 V. At this condition, the maximum duty cycle can be greater than 90%. Therefore, DMAX voltage must be modified in order to maintain desired maximum duty cycle. the resistors connected to the ICS pin. The amplitude of the VSC signal is same as the COSC pin voltage (4 V). For designs which use with SYNC pin, instead of VSC pin, the converter can still operate at duty cycles greater than 50% by generating an external slope compensation ramp using a simple RC circuit from the MOSFET driver output pin as shown on the application circuit. Over Current Protection Si9118/Si9119 are designed with a pulse-to-pulse peak current limiting protection circuit to protect itself, and the load in case of a failure. The voltage across the sense resistor is monitored continuously and if the voltage reaches its trigger level, the duty cycle is terminated. This limits the maximum current delivered to the load. In order to improve the accuracy of over current protection from traditional controllers, Si9118/Si9119 are designed with separate ILIMIT and ICS pins. Voltage on the ILIMIT pin does not sum in the traditional slope compensation voltage, which adds error into the detection level. ICS pin is used to sum the current sense signal and the slope compensation for loop stability. Output Driver Stage The DR pin is designed to drive a low-side n-channel MOSFET. The driver stage is sized to sink and source peak currents up to 500 mA with VCC = 12 V. This provides ample drive capability for 50 W of output power.
Slope Compensation Slope compensation is necessary for duty cycles greater than 50% to stabilize the inner current loop and maintain overall loop stability. In order to simplify the slope compensation circuitry, the Si9118 provides the buffered oscillator ramp signal, VSC to be used for external slope compensation. VSC is only available when DR is high. The VSC signal super-imposed with actual current sense signal should be used by the PWM comparator to determine the duty cycle. The summation of this signal should be fed into ICS pin. For optimum performance, proper slope compensation is required. The amount of slope compensation is determined by
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Document Number: 70815 S-60752--Rev. B, 05 Apr-99

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